1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (LCD) device and a method of fabricating the LCD device.
2. Discussion of the Related Art
Flat panel display devices have begun to replace cathode-ray tubes (CRTs) for information display applications. Various types of flat panel displays, such as liquid crystal display (LCD) devices, plasma display panels (PDPs), field emission displays (FEDs), and electro-luminescence displays (ELDs) have been developed to replace CRTs. Of these types of flat panel displays, LCD devices have many advantages, such as high resolution, light weight, thin profile, compact size, and low voltage power supply requirements.
In general, an LCD device includes two substrates that are spaced apart and opposite each other with a liquid crystal material interposed between the two substrates. The two substrates include electrodes facing each other such that a voltage applied between the electrodes induces an electric field across the liquid crystal material. Alignment of the liquid crystal molecules in the liquid crystal material changes proportionally with the intensity of the induced electric field in the direction of the induced electric field, thereby changing the light transmissivity of the LCD device. Thus, the LCD device displays images by varying the intensity of the induced electric field.
Recently, active matrix type LCD devices, which include thin film transistors (TFTs) and pixel electrodes arranged in matrix form, have been typically used. Hydrogenated amorphous silicon (a-Si:H) has been used as an active layer for the TFT because of its low temperature applications and because it is inexpensive. However, because the atoms in the hydrogenated amorphous silicon are randomly arranged, the bonds between the silicon atoms are weak and dangling. Accordingly, when light is irradiated or an electric field is induced, the silicon atom is in a quasi-stable state, thereby making the TFT unstable. The weak bonds also result in poor electrical properties. For example, the field effect mobility value is as low as 0.1 to 1.0 cm2/V·sec. Therefore, TFTs having amorphous silicon cannot reliably be used as switching devices.
In contrast, poly-crystalline silicon can be used for a driving circuit since poly-crystalline silicon has higher field effect mobility than does amorphous silicon.
FIGS. 1 and 2 are cross-sectional views, taken along a length direction and a width direction of a channel portion, respectively, illustrating an LCD device having a thin film transistor using poly-crystalline silicon according to the related art.
As illustrated in FIGS. 1 and 2, a buffer layer 18 is formed on a substrate 15. A semiconductor layer 23 of poly-crystalline silicon is formed on the buffer layer 18 in a switching region TrA. The entire semiconductor layer 23 has the same thickness. The semiconductor layer 23 has a channel portion 23a of intrinsic poly-crystalline silicon at the center of the semiconductor layer 23, and has ohmic contact portions 23b of impurity-doped poly-crystalline silicon at both sides of the semiconductor layer 23. When the impurity is n+ ions, the semiconductor layer 23 further has lightly doped drain (LDD) portions 23c, which have impurity concentrations lower than the ohmic contact portions 23b, between the ohmic contact layers 23b and the channel portion 23a. 
A gate insulating layer 28 is formed on the substrate 15 having the semiconductor layer 23. A gate electrode 35 is formed on the gate insulating layer 28 and corresponds to the channel portion 23a. 
An interlayer insulating film 43 is formed on the substrate 15 having the gate electrode 35. The interlayer insulating film 43 and the gate insulating layer 28 have semiconductor contact holes 45a and 45b exposing the ohmic contact portions 23b. Source and drain electrodes 48 and 53 are formed on the interlayer insulating film 43. The source and drain electrodes 48 and 53 contact the ohmic contact portions 23b through the semiconductor contact holes 45a and 45b. 
A passivation layer 60 is formed on the substrate 15 having the source and drain electrodes 48 and 53. The passivation layer 60 has a drain contact hole 63. A pixel electrode 65 is formed on the passivation layer 60 in a pixel region P. The pixel electrode 65 contacts the drain electrode 53 through the drain contact hole 63.
As explained above, the entire portions of the semiconductor layer 23 all have the same thickness. A side surface of an edge portion A of the semiconductor layer 23 has an angle θ1 equal to or more than 80 degrees with respect to a plane of the substrate 15.
Due to the structure of the semiconductor layer 23, step coverage of the gate insulating layer 28 is degraded. A step portion of the gate insulating layer 28 near the edge portion A of the semiconductor layer 23 has a thickness t2 thinner than a thickness t1 of other portions of the gate insulating layer 28. Accordingly, referring to FIG. 2, a step portion of the gate electrode 35 near the edge portion A of the semiconductor layer 23 has a thickness t3 thinner than a thickness t4 of other portions of the gate electrode 35.
Since the step portions of the gate insulating layer 28 and the gate electrode 35, corresponding to the edge portion A of the semiconductor layer 23, has the thickness t2 and t3 thinner than the thickness t1 and t4 of other portions of the gate insulating layer 28 and the gate electrode 35, strong electric fields due to the fringe field effect are induced at the edge portion A and a strong side current is generated along a width of the channel portion 23a. The side current disturbs the normally flowing drain current.
FIG. 3 is a graph illustrating a transfer curve of a gate voltage to a drain current in the LCD device according to the related art. In FIG. 3, a width of an LDD portion is 1 μm, and width and length of a channel portion are 4 μm and 4 μm.
When a gate voltage is applied within a range of 0V to 3V, drain current should linearly increase in order for a thin film transistor to operate normally. However, referring to FIG. 3, the side current due to the fringe field effect disturbs the flowing drain current. Accordingly, a hump i.e., a non-linear portion of the transfer curve, results.
The hump causes on/off time delays of the thin film transistor, and thus reliability of the thin film transistor is degraded.